//----------------------------------------------------------------------------- // // Digital Storage Scope (C Ver 1.1) // // Target Processor : SILABS C8051F007 ( 25MIPS ) // // // Copyright (C) 2001, 2005 SAMPLE Electronics co. // Programmed on 2005 SEP 31 // Designed by Junghoon Kim // // // TEL: (02) 701 - 8051 // FAX: (02) 701 - 8058 // Email: sample@korea.com // URL: HTTP://WWW.SAMPLE.CO.KR // //----------------------------------------------------------------------------- // // Attenuater Parameter Table // +------+-------+-------+-------+-------+-------+-------+-------+-------+ // | V/Div| 25mV | 50mV | 0.1V | 0.2V | 0.5V | 1.0V | 2.0V | 5.0V | // +------+-------+-------+-------+-------+-------+-------+-------+-------+ // | Full | 0.2V | 0.4V | 0.8V | 1.6V | 4.0V | 8.0V | 16V | 40V | // +------+-------+-------+-------+-------+-------+-------+-------+-------+ // | A.R. | 5/8 | 5/8 | 5/8 | 5/8 | /2 | /4 | /8 | /20 | // +------+-------+-------+-------+-------+-------+-------+-------+-------+ // | DACV | 0.15V | 0.3V | 0.6V | 1.2V | 2.4V | 2.4V | 2.4V | 2.4V | // +------+-------+-------+-------+-------+-------+-------+-------+-------+ // | Gain | 16 | 8 | 4 | 2 | 1 | 1 | 1 | 1 | // +------+-------+-------+-------+-------+-------+-------+-------+-------+ // | R-U | 300K | 300K | 300K | 300K | 500K | 1.5M | 3.5M | 9.5M | // +------+-------+-------+-------+-------+-------+-------+-------+-------+ // | R-D | 500K | 500K | 500K | 500K | 500K | 500K | 500K | 500K | // +------+-------+-------+-------+-------+-------+-------+-------+-------+ // // V/Div : Vertical Voltage Per Division // Full : Vertical Full Screen Voltage // A.R. : Attenuation Ratio // DACV : DAC Out Voltage (Shift Up Level = DACV / 2) // Gain : Internal Amplifier Gain // R-U : Attenuator Upper Side Register // R-L : Attenuator Lower Side Register ( 500 K Ohm Fixed ) // //----------------------------------------------------------------------------- // // Horizontal Time Base Constant Table // +------------+--------+------------------------+--------+ // | Time Base | Time | Timer 3 Reload Value | Ch Mode| // +------------+--------+------------------------+--------+ // | 500uS/Div | 10 uS | 65317 (65536 - 219) | Single | // +------------+--------+------------------------+--------+ // | 1mS/Div | 20 uS | 65317 (65536 - 219) | Both | // +------------+--------+------------------------+--------+ // | 2mS/Div | 50 uS | 64989 (65536 - 547) | Both | // +------------+--------+------------------------+--------+ // | 5mS/Div | 100 uS | 64441 (65536 - 1095) | Both | // +------------+--------+------------------------+--------+ // | 10mS/Div | 200 uS | 63336 (65536 - 2190) | Both | // +------------+--------+------------------------+--------+ // | 20mS/Div | 500 uS | 60061 (65536 - 5475) | Both | // +------------+--------+------------------------+--------+ // | 50mS/Div | 1 mS | 54586 (65536 - 10950) | Both | // +------------+--------+------------------------+--------+ // | 100mS/Div | 2 mS | 43636 (65536 - 21900) | Both | // +------------+--------+------------------------+--------+ // //----------------------------------------------------------------------------- // #include "xstdsys.h" #include #include // #define RELAY_5V 0x20; // 00100000 Vertical 5V / Division #define RELAY_2V 0x10; // 00010000 Vertical 2V / Division #define RELAY_1V 0x08; // 00001000 Vertical 1V / Division #define RELAY_P5 0x04; // 00000100 Vertical 500mV / Division #define RELAY_MV 0x02; // 00000010 Vertical 200mV, 100mV, 50mV, 25mV / Division #define RELAY_OFF 0x00; // 00000000 // #define AC_mode 0x0; // 0 AC Input Mode #define DC_mode 0x1; // 1 DC Input Mode // #define TB500US 65317 // 500 uS/Div 10 uS Only Single Channel #define TB1MS 65317 // 1 mS/Div 20 uS #define TB2MS 64989 // 2 mS/Div 50 uS #define TB5MS 64441 // 5 mS/Div 100 uS #define TB10MS 63336 // 10 mS/Div 200 uS #define TB20MS 60061 // 20 mS/Div 500 uS #define TB50MS 54586 // 50 mS/Div 1 mS #define TB100MS 43636 // 100 mS/Div 2 mS #define TB200MS 21736 // 200 mS/Div // #define DAC_25MV 0x00FF // 25 mV/Div #define DAC_50MV 0x01FF // 50 mV/Div #define DAC_100MV 0x03FF // 100 mV/Div #define DAC_200MV 0x07FF // 200 mV/Div #define DAC_500MV 0x0FFF // 500 mV/Div #define DAC_1V 0x0FFF // 1 V/Div #define DAC_2V 0x0FFF // 2 V/Div #define DAC_5V 0x0FFF // 5 V/Div // #define ADG_25MV 0x04 // 25 mV/Div Gain = 16 #define ADG_50MV 0x03 // 50 mV/Div Gain = 8 #define ADG_100MV 0x02 // 100 mV/Div Gain = 4 #define ADG_200MV 0x01 // 200 mV/Div Gain = 2 #define ADG_500MV 0x00 // 500 mV/Div Gain = 1 #define ADG_1V 0x00 // 1 V/Div Gain = 1 #define ADG_2V 0x00 // 2 V/Div Gain = 1 #define ADG_5V 0x00 // 5 V/Div Gain = 1 // #define ADC_SAR 0x40 // 0b10000000 ADC SAR 4 System Clocks #define BOTHCH 0x00 // Ch1: Ch2: Both Sampling and Data Out #define ONLYCH1 0x01 // Ch1: Only Sampling and Data Out #define ONLYCH2 0x02 // Ch2: Only Sampling and Data Out // #define HIGH >>8 & 0x00FF // High Byte in Word(16 bit) #define LOW & 0x00FF // Lower Byte in Word(16 bit) // #define BUFFER_SIZE 0x0800 // Buffer Size // _sfrbit hc595_ser_ch1 = _p0^2; // Ch1 Attenuater _sfrbit hc595_srclk_ch1 = _p0^3; _sfrbit hc595_rclk_ch1 = _p0^4; // _sfrbit hc595_ser_ch2 = _p0^5; // Ch2 Attenuater _sfrbit hc595_srclk_ch2 = _p0^6; _sfrbit hc595_rclk_ch2 = _p0^7; // Gloval Variable _bit gnd_a; // Ch 1 State 1: Connect 0: GND (Open) _bit gnd_b; // Ch 2 State 1: Connect 0: GND (Open) _bit in_mode_a; // Ch 1 Input Mode 1: DC 0: AC _bit in_mode_b; // Ch 2 Input Mode 1: DC 0: AC // unsigned char adc_gain_a; // Ch A ADC Configuration PGA Gain & Clock Rate unsigned char adc_gain_b; // Ch B ADC Configuration PGA Gain & Clock Rate unsigned char attn_a; // Ch A Attenuator unsigned char attn_b; // Ch B Attenuator unsigned char ch_mode; // Channel Sampleing and Data Out Mode unsigned int xpoint; // External Memory Buffer Pointer // unsigned char _xdata buffer[BUFFER_SIZE]; // External Buffer Memory // //////////////////////////////////////////////////////// void _interrupt IVN_ADC0CONVERSION adc0_end_of_conversion() { // ADC 0 Conversion _adcint = 0; // Clear ADC Interrupt Flag buffer[xpoint + 0x00] = _adc0h; buffer[xpoint + 0x01] = _adc0l; if(ch_mode == BOTHCH) { if (xpoint & 0x0002) { _amx0sl = 0x00; _adc0cf = adc_gain_a | ADC_SAR; } else { _amx0sl = 0x02; _adc0cf = adc_gain_b | ADC_SAR; } xpoint += 0x0002; } if (ch_mode == ONLYCH1) { _amx0sl = 0x00; _adc0cf = adc_gain_a | ADC_SAR; xpoint += 0x0004;} if (ch_mode == ONLYCH2) { _amx0sl = 0x02; _adc0cf = adc_gain_b | ADC_SAR; xpoint += 0x0004;} } //////////////////////////////////////////////////////// static _bit _bByteReceived; static unsigned char _nReceivedCharacter; static _bit _bByteTransmitting; void _interrupt IVN_SERIALPORT0 Uart0Interrupt() { if (_ri) { _ri = 0; _nReceivedCharacter = _sbuf; _bByteReceived = 1; } if (_ti) { _ti = 0; _bByteTransmitting = 0; } } int putch(int c) { if (c == '\n') { while (_bByteTransmitting); _sbuf = '\r'; _bByteTransmitting = 1; } while (_bByteTransmitting); _bByteTransmitting = 1; _sbuf = c; return c; } int getch() { while (!_bByteReceived); _bByteReceived = 0; return (int)_nReceivedCharacter; } //////////////////////////////////////////////////////// void set_atten_1(void) { unsigned char i, j; i = 0; if (gnd_a) { i = attn_a; if (in_mode_a) { i = i | 0x01; } } hc595_rclk_ch1 = 0; for (j = 0; j < 8; j++) { hc595_srclk_ch1 = 0; hc595_ser_ch1 = 0; if (i & 0x80) { hc595_ser_ch1 = 1; } hc595_srclk_ch1 = 1; i = i<<1; } hc595_rclk_ch1 = 1; } void set_atten_2(void) { unsigned char i, j; i = 0; if (gnd_b) { i = attn_b; if (in_mode_b) { i = i | 0x01; } } hc595_rclk_ch2 = 0; for (j = 0; j < 8; j++) { hc595_srclk_ch2 = 0; hc595_ser_ch2 = 0; if (i & 0x80) { hc595_ser_ch2 = 1; } hc595_srclk_ch2 = 1; i = i<<1; } hc595_rclk_ch2 = 1; } void set_timer3(unsigned int t) { unsigned char u, v; _eie2 = _eie2 & 0xFE; // Disable Timer 3 Interrupts _tmr3cn = 0x02; // Stop Timer, Clear Overflow Flag TF3 u = t & 0xFF; v = (t>>8) & 0xFF; _tmr3rll = u; // Timer 3 Reload Low _tmr3rlh = v; // Timer 3 Reload High _tmr3l = u; _tmr3h = v; } void nibleout(unsigned char c) { unsigned char d; d = c & 0x0F; if (d < 0x0A) { d = d | 0x30; } else { d = d + 0x37; } putch(d); } ////////////////////////////////////////////////////// main() { unsigned char c, d, e; _dac0l = 0xFF; // DAC0 Lower Byte _dac0h = 0x0F; _dac1l = 0xFF; // DAC1 Lower Byte _dac1h = 0x0F; _amx0cf = 0x00; // Single Ended Input Mode _amx0sl = 0x00; _adc0cn = 0xC5; in_mode_a = AC_mode; // Ch1: AC Mode in_mode_b = AC_mode; // Ch2: AC Mode gnd_a = 0; // Ch1: GND gnd_b = 0; // Ch2: GND attn_a = RELAY_OFF; // Ch1: All Relay OFF attn_b = RELAY_OFF; // Ch2: All Relay OFF set_atten_1(); // Ch1: Attenuater Set set_atten_2(); // Ch2: Attenuater Set ch_mode = BOTHCH; // Ch1 and Ch2 Alternate Mode set_timer3(TB10MS); // Horizental Time Base Set while (1) { c = getch(); if (c == 'U') { in_mode_a = 1; gnd_a = 1; set_atten_1(); } // Ch1: DC Input Mode if (c == 'V') { in_mode_a = 0; gnd_a = 1; set_atten_1(); } // AC Input Mode if (c == 'W') { in_mode_a = 0; gnd_a = 0; set_atten_1(); } // GND (0V) Mode if (c == 'u') { in_mode_b = 1; gnd_b = 1; set_atten_2(); } // Ch2: DC Input Mode if (c == 'v') { in_mode_b = 0; gnd_b = 1; set_atten_2(); } // AC Input Mode if (c == 'w') { in_mode_b = 0; gnd_b = 0; set_atten_2(); } // GND (0V) Mode if (c == 'B') { adc_gain_a = ADG_25MV; _dac0l = DAC_25MV LOW; // Ch1: Attenuater _dac0h = DAC_25MV HIGH; attn_a = RELAY_MV; set_atten_1(); } // 25 mV/Div if (c == 'C') { adc_gain_a = ADG_50MV; _dac0l = DAC_50MV LOW; _dac0h = DAC_50MV HIGH; attn_a = RELAY_MV; set_atten_1(); } // 50 mV/Div if (c == 'D') { adc_gain_a = ADG_100MV; _dac0l = DAC_100MV LOW; _dac0h = DAC_100MV HIGH; attn_a = RELAY_MV; set_atten_1(); } // 100 mV/Div if (c == 'E') { adc_gain_a = ADG_200MV; _dac0l = DAC_200MV LOW; _dac0h = DAC_200MV HIGH; attn_a = RELAY_MV; set_atten_1(); } // 200 mV/Div if (c == 'F') { adc_gain_a = ADG_500MV; _dac0l = DAC_500MV LOW; _dac0h = DAC_500MV HIGH; attn_a = RELAY_P5; set_atten_1(); } // 500 mV/Div if (c == 'G') { adc_gain_a = ADG_1V; _dac0l = DAC_1V LOW; _dac0h = DAC_1V HIGH; attn_a = RELAY_1V; set_atten_1(); } // 1 V/Div if (c == 'H') { adc_gain_a = ADG_2V; _dac0l = DAC_2V LOW; _dac0h = DAC_2V HIGH; attn_a = RELAY_2V; set_atten_1(); } // 2 V/Div if (c == 'I') { adc_gain_a = ADG_5V; _dac0l = DAC_5V LOW; _dac0h = DAC_5V HIGH; attn_a = RELAY_5V; set_atten_1(); } // 5 V/Div if (c == 'b') { adc_gain_b = ADG_25MV; _dac1l = DAC_25MV LOW; // Ch2: Attenuater _dac1h = DAC_25MV HIGH; attn_b = RELAY_MV; set_atten_2(); } // 25 mV/Div if (c == 'c') { adc_gain_b = ADG_50MV; _dac1l = DAC_50MV LOW; _dac1h = DAC_50MV HIGH; attn_b = RELAY_MV; set_atten_2(); } // 50 mV/Div if (c == 'd') { adc_gain_b = ADG_100MV; _dac1l = DAC_100MV LOW; _dac1h = DAC_100MV HIGH; attn_b = RELAY_MV; set_atten_2(); } // 100 mV/Div if (c == 'e') { adc_gain_b = ADG_200MV; _dac1l = DAC_200MV LOW; _dac1h = DAC_200MV HIGH; attn_b = RELAY_MV; set_atten_2(); } // 200 mV/Div if (c == 'f') { adc_gain_b = ADG_500MV; _dac1l = DAC_500MV LOW; _dac1h = DAC_500MV HIGH; attn_b = RELAY_P5; set_atten_2(); } // 500 mV/Div if (c == 'g') { adc_gain_b = ADG_1V; _dac1l = DAC_1V LOW; _dac1h = DAC_1V HIGH; attn_b = RELAY_1V; set_atten_2(); } // 1 V/Div if (c == 'h') { adc_gain_b = ADG_2V; _dac1l = DAC_2V LOW; _dac1h = DAC_2V HIGH; attn_b = RELAY_2V; set_atten_2(); } // 2 V/Div if (c == 'i') { adc_gain_b = ADG_5V; _dac1l = DAC_5V LOW; _dac1h = DAC_5V HIGH; attn_b = RELAY_5V; set_atten_2(); } // 5 V/Div if (c == '0') { ch_mode = ONLYCH1; set_timer3(TB500US); } // Time Base 500 uS/Div Only Ch1 if (c == '1') { ch_mode = ONLYCH2; set_timer3(TB500US); } // Time Base 500 uS/Div Only Ch2 if (c == '2') { ch_mode = BOTHCH; set_timer3(TB1MS); } // Time Base 1 mS/Div Both if (c == '3') { ch_mode = BOTHCH; set_timer3(TB2MS); } // Time Base 2 mS/Div Both if (c == '4') { ch_mode = BOTHCH; set_timer3(TB5MS); } // Time Base 5 mS/Div Both if (c == '5') { ch_mode = BOTHCH; set_timer3(TB10MS); } // Time Base 10 mS/Div Both if (c == '6') { ch_mode = BOTHCH; set_timer3(TB20MS); } // Time Base 20 mS/Div Both if (c == '7') { ch_mode = BOTHCH; set_timer3(TB50MS); } // Time Base 50 mS/Div Both if (c == '8') { ch_mode = BOTHCH; set_timer3(TB100MS); } // Time Base 100 mS/Div Both if (c == '9') { ch_mode = BOTHCH; set_timer3(TB200MS); } // Time Base 200 mS/Div Both if (c == 'S') { // Start _adc0cf = adc_gain_a; // Start Gain if ((ch_mode == ONLYCH1) || (ch_mode == BOTHCH)) { xpoint = 0x0000; // Buffer Start Address Set _amx0sl = 0x00; // Start Channel 1 } if (ch_mode == ONLYCH2) { xpoint = 0x0002; // Buffer Start Address Set _amx0sl = 0x02; // Start Channel 2 } _adcen = 1; // Enable ADC _eie2 = _eie2 | 0x02; // Enable ADC end of Conversion Interrupt _tmr3cn = _tmr3cn | 0x04; // Set TR3 Timer Run bit while (xpoint < BUFFER_SIZE) ; // Wait Until Conversion Complete _adcen = 0; _eie2 = _eie2 & 0xFD; _tmr3cn = _tmr3cn & 0xFB; xpoint = 0; while (xpoint < BUFFER_SIZE) { // Buffer Data Out d = buffer[xpoint++]; e = d; d = d>>4; nibleout(d); nibleout(e); } putch('\n'); // CR, LF Code Out } } } /////////////////////////// End of FILE //////////////////////